XC2C128-7VQG100I

• Cool Runner-II CPLD, 128 macrocells, 8 Logic blocks, Approximately 3000 Gates
• 80 User I/O Pins
• 100-Pin TQFP package, 14 Mm X 14 mm, 1 Mm Height
• Speed Grade 7: 7.5 Ns Propagation delay, 119 MHz Maximum Frequency
• 1.8 V Core Supply (1.7 V to 1.9 V range)
• Industrial Temperature Range -40 C to +85 C
• RoHS compliant, Tin Contact plating, Surface Mount

The AMD XC2C128-7VQG100I is a Cool Runner-II family CPLD with 128 macrocells, roughly 3000 usable gates and 80 user I/O, housed in a 100-pin TQFP/VTQFP package measuring 14 mm x 14 mm. It is a speed grade 7 device with 7.5 ns pin-to-pin propagation delay and 119 MHz maximum frequency, running from a 1.8 V core supply (1.7 V to 1.9 V) across an industrial -40 C to +85 C temperature range. CPLDs use non-volatile configuration, so the XC2C128-7VQG100I is available immediately at power-up without an external boot device.

CPLDs of this size handle the glue logic that sits around a processor or FPGA: power sequencing and reset supervision, bus and level translation, address decoding, LED and front-panel control, and small state machines that must be valid the instant the board powers on. The industrial temperature grade and instant-on configuration make the XC2C128-7VQG100I common in industrial automation, telecom line cards, medical instruments and long-lifecycle embedded platforms. Because Cool Runner-II designs are frequently locked into products with 10-plus year production runs, sustaining buyers and repair programs are a significant part of demand for this device.